How Central Processing Unit (CPU) Control Everything

 All things in all posts will help you visualize about the way that computers work generally. Note that it is not the real structure of modern computers, but the way that modern computers work is nearly the same as in my posts. I am sure that if you understand about the way that computers work in my posts, you will easy to learn about all fields of computer afterward. Thank you !!!

We have just learned about the clock and the stepper in the control unit of the central processing unit (CPU). Look at the diagram below again to recall the position and function of the control unit:

Now, we know about all components of the control unit that control the transmitting and receiving the byte of data among devices through “enable” bits and “set” bits. Now, we will organize those components into a structure that has a clear function. Let’s look at the diagram below first:

We have the clock with three outputs along with a stepper on the top of this structure. Because this structure will control the transmitting and receive byte of data among devices, we must have parts for “enable” bits and “set” bits. We will arrange the “set” bits part on the right and the “enable” bits part on the left. 

You can see that all the “enable” bits of devices that are registers, RAM,...will connect to the output of AND gates that have two inputs. One input of these AND gates will come from the “clk e” bit of the clock and one input will come from step bits of the stepper such as “step 1”, “step 2”,...So, you can see that each device will be enabled in specific cycles of clock.

You can also see that all the “set” bits of devices that are registers, RAM,...will connect to the output of AND gates that have two inputs. One input of these AND gates will come from the “clk s” bit and one input will come from step bits of the stepper such as “step 1”, “step 2”,...So, you can see that each device will be set in specific cycles of clock.

For example, when we want to transmit the byte of data in ACC register to R0 register in one cycle of clock like “step 6”, we will connect all wires from “step 6” bit to the AND gate for “enable” bit of ACC and to AND gate for “set” bit of R0.

When the clock is “on” in the sixth cycle, the “step 6” bit is “on” and one input of two AND gates will “on” immediately. What about the “clk e” bit and “clk s” bit inputs of two AND gates? As you know, the action time of “clk e” and “clk s” in one cycle of clock as below:

So, the “clk e” will be “on” first and so the output of the AND gate for “enable” bit of ACC will be “on” first. The byte of data in the ACC will have time to be on the bus. Then, the “clk s” will be “on” and the output of the AND gate for the “set” bit of R0 will be “on”. The byte of data on the bus will be saved in R0. The “clk s” will be “off” before the “clk e” “off”, so the byte of data in ACC will be saved in R0 forever if the “set” bit of R0 does not “on” again.

It is the way exactly that all data of byte in the computers will be transported and received. The “to ALU” part we will examine later. It is another part of the control unit that is related to “op” code for ALU (arithmetic and logic unit).

Now, everything is available, we can connect wires properly to perform some useful function for this structure. And we will discuss this in next posts. You need to review everything that you do not understand so far to come to many complex parts later. I hope you like this post. Thanks for reading and see you later!!!